1. Field of the Invention
The present invention relates to a dielectrically-isolated semiconductor integrated circuit in which two or more bonding wires are connected to semiconductor chips having a dielectrically-isolated structure (hereinafter called "DI structure") and, more particularly, a dielectrically-isolated semiconductor integrated circuit which is able to achieve less variation in characteristics due to underloop of bonding wires and which is to be manufactured with high reliability at low cost.
2. Description of the Prior Art
A device isolation step in manufacturing steps of the semiconductor integrated circuit corresponds to steps of defining regions in which respective elements (e.g., a diode or a transistor) constituting an integrated circuit are formed and isolating adjacent elements to insulate them electrically. A DI structure may be considered as one of device isolation structures. Such DI structure is a structure wherein the elements are isolated by a dielectric substance such as oxide film.
An optical semiconductor switch, or the optical coupler using the DI structure in the prior art will be explained hereinbelow. The ordinary optical semiconductor switch comprises a light emitting diode (referred to as "LED" simply hereinafter) as a light emitting device, a photodiode array as a light receiving device, an impedance component connected in parallel with the photodiode array, and a metal oxide semiconductor field effect transistor (referred to as "MOSFET" simply hereinafter) in which a gate G and a source S are connected to an anode and a cathode of the photodiode array respectively. As a result, the impedance component is connected between the gate and source of the MOSFET. In a hybrid IC structure that is well known, the photodiode array and the impedance element are integrated in a first semiconductor chip while the MOSFET is integrated in a second semiconductor chip, and both semiconductor chips are mounted on a predetermined substrate or a lead frame and then connected by bonding wires.
The optical semiconductor switch generates an optical electromotive force across the photodiode array by turning on the LED and irradiating the emitted light on the photodiode array. Then the optical electromotive force generated in the photodiode array is applied between the gate G and the source S of the MOSFET to render the MOSFET conductive (turn-on state). In contrast, the switch ceases the optical electromotive force generated in the photodiode array by turning off the LED, and discharges charges accumulated in an electrostatic capacitance between the gate G and the source S of the MOSFET via the impedance component connected in parallel with the photodiode array to render the MOSFET nonconductive (turn-off state). In this manner, a switching operation of the MOSFET is carried out by turning the LED on and off.
FIG. 1A is a perspective view showing a schematic structure of four photodiode array chips (first semiconductor chip) 9 immediately after the wafer is cut out by dicing. As shown in FIG. 1A, each photodiode array chip 9 has the DI structure wherein a plurality of Si islands 25 serving as active regions in which photodiodes constituting the photodiode array are formed in a one-by-one correspondence. Each active region is isolated by an isolation film (isolation oxide film) 49 made of a dielectric substance. Further, a polysilicon film 27 (sheet resistance: 1 M.OMEGA./.quadrature.) is buried in the isolation groove between the n type Si islands 25 to planarize a surface of the chip.
In order to constitute the optical semiconductor switch, the first semiconductor chip shown in FIG. 1A and the second semiconductor chip in which the MOSFET is integrated are mounted on the predetermined substrate or the lead frame. Usually, the semiconductor chip is fabricated in such a manner that plural same circuit patterns are formed on one sheet of wafer by lithography technique such as by using a stepper and respective circuit patterns are cut out along dicing lines and divided in a predetermined size. A plurality of photodiode array chips 9 shown in FIG. 1A are obtained by cutting along the dicing line 29 around the respective chips.
Bonding pads serving as electrodes for connecting the chips and the bonding wires used as external lead lines are formed on the first semiconductor chip (photodiode array chip) 9 and the second semiconductor chip (MOSFET chip), though not shown. Although metal layers. etc. on the surface are omitted from FIG. 1A, practically the anode pad to which the anode of the photodiode is to be connected and the cathode pad to which the cathode of the photodiode is to be connected are formed on the photodiode array chip. On the other hand, the gate pad to which the gate G of the MOSFET is to be connected, the source pad to which the source of the MOSFET is to be connected, and the drain pad to which the drain of the MOSFET is to be connected are formed on the MOSFET chip. Still further, in order to connect electrically the photodiode array chip 9 to the MOSFET chip (not shown), the anode pad and the cathode pad formed on the photodiode array chip 9 are connected to the gate pad and the source pad formed on the MOSFET chip via two bonding wires respectively.
As shown in FIG. 1B, one of the photodiode array chips shown in FIG. 1A is mounted on a substrate 91 by adhesive 92 (or solder) after the dicing process. FIG. 1B is a sectional view showing the photodiode array chip 9 in the prior art after wire bonding is implemented. Because of deformation, etc. due to variation in assembling steps or a temperature cycle test, as shown in FIG. 1B, it is likely to cause underloop of two bonding wires 21, 23. At this time, if both the bonding wires 21, 23 come into contact with edges of the chip (indicated by A and B in FIG. 1B), parasitic resistance (parasitic conductance) occurs between the anode pad 13 and the cathode pad 15 of the photodiode array via the polysilicon film 27 since different potential is applied to the bonding wires 21, 23. FIG. 1C is an equivalent circuit diagram showing the parasitic resistance 5a at a case that underloop of the bonding wires is caused in the optical semiconductor switch in the prior art. In FIG. 1C, a reference 1 denotes the LED, and 7, the MOS FET. The impedance component 5 and the parasitic resistance (parasitic conductance) 5a are connected in parallel with the photodiode array 3.
The problem arising in the optical semiconductor switch in the prior art will be discussed in detail with reference to FIG. 1C. For instance, in the event that the impedance component 5 is designed as several M.OMEGA., switching speed of the optical semiconductor switch is given as several hundreds .mu.s and I.sub.FT (input current) to the LED 1 is about 1 mA. However, if the parasitic resistance (parasitic conductance) 5a occurs, a total impedance component between the anode A and the cathode K of the photodiode array 3 is determined by the parasitic resistance and lowered to several tens k.OMEGA.. For this reason, an output of the LED 1 must be enhanced so that I.sub.FT is increased up to about 10 mA. Therefore, if the parasitic resistance 5a has occurred, a normal input current fails to operate the optical semiconductor switch. Since underloop of the bonding wires shown in 1B is highly generated on the secondary side of the bonding, such underloop becomes an issue particularly if the anode pad 13 and the cathode pad 15 of the photodiode array chip 9 are connected on the secondary side by wedge type bonding or stitch type bonding.
As a method to overcome the problem in the prior art, it may be considered to form an insulating coating film on a surface of the bonding wire. But there has been another problem to cause degradation in bonding strength. Further the manufacturing cost of the semiconductor device increases, since material of the insulating coating film causes inferior contact between the bonding wire and the metal for the bonding pad and the coating film requires additional steps making the bonding technique complicated.